SPICE Model
PDK
Standard Cell
Advanced Logic Simulator
Equipped with high-performance simulation engines and constraint solvers to enhance compile time efficiency for large SoC designs
Supports a wide array of languages, including Verilog, VHDL, SystemVerilog, SystemC, and their combinations
Integrates Universal Verification Methodology (UVM) to enable rapid verification testbench setup
Provides extensive features for function, assertion and code coverage testing
Assertion-based verification facilitates the early detection and rectification of potential design flaws, compressesing the verification timeline and expediting the time-to-market
Added security through encryption algorithms to safeguard customer IP
Integrates with transistor-level NanoSpice simulators to provide complete mixed signal verification solutions
Innovated optimization from compilation,
simulation to constraint solver engines
X-state propagation and
race condition elimination
Easy to use and quick migration
from existing tools
Supports both X86 and
ARM platforms
Native integration with NanoSpice
for mixed signal verification
Digital circuits
from behavioral,
RTL to gate
level with SDF
Mixed signal SoC
full chip verification
by integrating
NanoSpice
SystemVerilog
and SystemC
mixed language
testbench
Testbench
setup
in system
verification
