SPICE Model
PDK
Standard Cell
Hierarchical SoC Design Planning Solution
Constraints-driven RTL design floorplanning for better QoR
Addresses complexity problem of SoC design via intelligent partitioning of the full chip into many blocks or sub-systems
Chip partitioning includes physical hierarchical partitions of the design and pin placement of each sub-system
Accurate estimation of the bus interconnect timing between sub-systems
Mixed-level design planning (RTL/Gate/Black-box)
Flexible design abstraction management
Rich sets of key engineering features
Automatic block pin assignment &
bus interconnect planning
Efficient RTL design planning with minimum efforts for input data preparation
Reducing design TAT
by minimization of design iterations
Large & complex
SoC design
Design & constraints exploration
Constraints-driven floorplanning
Automatic/manual
pin assignment
Routing congestion estimation
BUS interconnect planning
Hierarchical floorplanning
